Microcomputers typically have the capacity for making requests for data and for instructions before the actual requested information is needed. These requests are prioritized by some established criteria. A major criterion typically is the order in which the requests are received. There are cases, however, in which it would be desirable to have data requests have a higher priority than might ordinarily be assigned. Such cases typically occur when a number of data cycles are going to be consecutively run. One example is operating with a co-processor in which there will be a lengthly exchange of data. During this time, if the external bus interface of the microcomputer was dedicated to data operations, time could be saved. In state of the art microcomputers, however, priority is such that, after each operation, either the data exchange is potentially disrupted by an instruction request which should have a lower priority, or time is lost recalculating priority after such external bus operation. This resulted in wasting time between desired data bus cycles for either determining priority or running an undesired bus cycle.